1. Field of the Invention
The invention relates in general to a method of fabricating an integrated circuit (IC). More particularly, this invention relates to a method of preventing the threshold voltage of a metal-oxide semiconductor (MOS) transistor from being reduced by shallow trench isolations.
2. Description of the Related Art
A typical integrated circuit includes a peripheral circuit and a core circuit. The peripheral circuit is designed for input/output operations, while the core circuit executes major functions of the integrated circuit. By assembling the peripheral circuit and the core circuit on a single chip, the peripheral circuit is required to bear a relatively larger operation voltage. Therefore, the gate oxide layer formed in the peripheral circuit region is typically thicker than the gate oxide layer formed in the device region comprising the core circuit. For example, when a voltage of 3.3 volts is applied to a gate in the peripheral circuit region, the thickness of the gate oxide thereof is about 80 angstroms and the threshold voltage is about 0.8 volts. In contrast, when a voltage of 2.5 volts is applied to the gate with a threshold voltage of about 0.5 volt in the core circuit region, a required thickness of the gate oxide is about 55 angstroms. In addition, compared to the peripheral circuit region, the device density of the core circuit region is typically higher, which results in a smaller linewidth of gate and a smaller channel width. The threshold voltage is thus seriously decreased.
FIG. 1A is a top view of a conventional shallow trench isolation, and FIG. 1B is a cross-sectional view cutting along the line I-I′ of FIG. 1B. In a silicon substrate 100, a shallow trench isolation 102 is formed in a periphery of an active region 108. A polysilicon gate 104 is formed on the substrate 100 and the shallow trench isolation 102. An electric field between the polysilicon gate 104 and the silicon substrate 100 is generated while applying a voltage to the polysilicon gate 104. The electric field is more significantly distributed near an edge 106 of the shallow trench isolation 102 under the polysilicon gate 104. As a result, a higher leakage current is generated near the edge 106 of the shallow trench isolation 102 when the transistor is off As a result, the threshold voltage for turning on the transistor is decreased.
For MOS transistors with a gate linewidth of less than 0.25 microns, as the channel width 112 is decreased, the proportion of channel width 112 formed by the edge 106 of the active region 108 is increased. Consequently, the edge 106 affects the decrease of threshold voltage to cause a further decreased threshold voltage of the transistor.
In FIG. 2, when a channel width is 5 microns in a PMOS transistor with a gate linewidth (equivalent to channel length) of 0.18 microns, the threshold voltage is about 0.35 volts to about −0.31 volts. When the channel width is shrunk to 1 micron, the threshold voltage is further reduced to between −0.33 volts and −0.28 volts. With a further shrinkage of the channel width to 0.3 micron to 0.2 micron, the threshold voltage ranges between −0.32 volts and −0.21 volts.
In FIG. 3, when the gate linewidth of an NMOS transistor is about 0.18 micron, the threshold voltage for a channel width of 5 microns is between 0.41 volts and 0.34 volts. When the channel width is reduced to 1 micron, the threshold voltage is reduced to between 0.40 and 0.31 volts. With a further shrinkage of the channel width to between 0.3 and 0.2 microns, the threshold voltage is reduced to between 0.37 and 0.22 volts.
As shown in FIG. 2 and FIG. 3, the threshold voltage is reduced as the channel width shrinks. However, ideally, the threshold voltage is not affected by the channel width. For example, a MOS transistor with a channel width of 5 micron is expected to have a threshold voltage the same as that of the MOS transistor with a smaller channel width.
Prior technique has employed methods such as rounding oxidation, spacer protection and nitride pull back to modify the silicon substrate close to the edge of the shallow trench isolation, so as to minimize the local electric field. However, the above fabrication processes are complex and difficult to control.